This invention relates generally to display devices and particularly to a shift register for the select line circuitry of an active matrix liquid crystal display device.
A liquid crystal display is composed of a matrix of liquid crystal pixels which are arranged vertically in columns and horizontally in rows. When a full color display is desired, and particularly when a gray scale display is needed to display color video, each of the liquid crystal pixels is composed of three elements which individually provide red, green and blue light. In a gray scale video display the individual pixel elements are biased to various voltages to control the brightnesses of the colors provided by each of the elements, and thus all colors can be produced, including flesh tones. The video information is applied to the display pixels by data lines which apply the proper voltage levels to the individual pixel elements within the columns to achieve the desired colors for the various pixels. The full display is produced by sequentially actuating the various horizontal lines using a select scanner circuit so that the display is produced one horizontal line at a time. In an active matrix liquid crystal display, each of the individual pixel elements is associated with a thin film transistor (TFT) which is used to turn the pixel element on and off. The source of the TFT is coupled to the data line over which the video information is supplied, while the gate electrode of the TFT is coupled to the select line which is energized by the select line scanner.
Frequently, the TFTs associated with the individual pixel elements are fabricated using either polysilicon or amorphous silicon technology. Preferably the drive circuitry used to apply the video information to the pixel elements, and the select scanner circuitry used to select the horizontal lines, are fabricated on the same substrate as the pixel elements and simultaneously with the TFTs. Accordingly, when amorphous silicon technology is used the components are fabricated with low mobility unstable enhancement type n-channel transistors. There are several problems associated with fabricating circuitry with this technology. First, the performance of the devices is inherently slow because of the low carrier mobility and also because of the high gate overlap capacitance. Second, there is no circuit voltage gain because of the lack of a stable load device. Third, the threshold voltage of the transistors is unstable even under modest voltage and temperature stress conditions. The threshold voltage instability presents a particularly severe problem with the select line scanners because of the need for much higher output voltages. Typically, these output voltages are 20 volts peak-to-peak rather than 5 volts peak-to-peak as they are for the data line scanners. Conventional NMOS shift register circuits are not adequate to meet either the speed or stability requirements for the select line scanner shift registers. The present invention overcomes these difficulties.